technical data iw4029b presettable up/down counter high-voltage silicon-gate cmos rev. 00 the iw4029b consists of a four-s tage binary or bcd-decade up/down counter with provisions for look-ahead carry in both counting modes. the inputs consists of a single clock, carry in,(clock enable), binary/decade, up/down, preset enable, and four individual jam signals. q1, q2, q3, q4 and a carry out signal are provided as outputs. a high preset enable signal allows information on the jam inputs to preset the counter to any state asynchronously with the clock. a low on each jam line, when th e preset-enable signal is high, resets the counter to its zero count. the counter is advanced one count at the positive transition of the clock when the carry in and preset enable signals are low. advancement is inhibited when the carry in or preset enable signals are high. the carry out signal is normally high and goes low when the counter reaches its maximum count in the up mode or the minimum count in the down mode provided the carry in signal is low. the carry in signal in the low state can thus be considered a clock enable. the carry in terminal must be connected to gnd when not in use. ordering information iw4029bn plastic IW4029BD soic t a = -55 to 125 c for all packages pin assignment binary counting is accomplishe d when the binary/decade input is high; the c ounter counts in the decade mode when the binary/decade input is low. the counter counts up when the up/down input is high, and down when the up/down input is low. parallel clocking provides synchronous control and hence faster response from all counting outputs. ripple-clocking allows for longer clock input rise and fall times. ? operating voltage range: 3.0 to 18 v ? maximum input current of 1 a at 18 v over full package- temperature range; 100 na at 18 v and 25 c ? noise margin (over full p ackage temperature range): 1.0 v min @ 5.0 v supply 2.0 v min @ 10.0 v supply 2.5 v min @ 15.0 v supply logic diagram pin 16=v cc pin 8= gnd
iw4029b rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +20 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 10 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw p d power dissipation per output transistor 100 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 3.0 18 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c this device contains protection circuitry to guard agains t damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
iw4029b rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v -55 c 25 c 125 c unit v ih minimum high-level input voltage v out = 0.5 v or v cc - 0.5v v out = 1.0 v or v cc - 1.0 v v out = 1.5 v or v cc - 1.5v 5.0 10 15 3.5 7 11 3.5 7 11 3.5 7 11 v v il maximum low - level input voltage v out = 0.5 v or v cc - 0.5v v out = 1.0 v or v cc - 1.0 v v out = 1.5 v or v cc - 1.5v 5.0 10 15 1.5 3 4 1.5 3 4 1.5 3 4 v v oh minimum high-level output voltage v in =gnd or v cc 5.0 10 15 4.95 9.95 14.95 4.95 9.95 14.95 4.95 9.95 14.95 v v ol maximum low-level output voltage v in =gnd or v cc 5.0 10 15 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 v i in maximum input leakage current v in = gnd or v cc 18 0.1 0.1 1.0 a i cc maximum quiescent supply current (per package) v in = gnd or v cc 5.0 10 15 20 5 10 20 100 5 10 20 100 150 300 600 3000 a i ol minimum output low (sink) current v in = gnd or v cc u ol =0.4 v u ol =0.5 v u ol =1.5 v 5.0 10 15 0.64 1.6 4.2 0.51 1.3 3.4 0.36 0.9 2.4 ma i oh minimum output high (source) current v in = gnd or v cc u oh =2.5 v u oh =4.6 v u oh =9.5 v u oh =13.5 v 5.0 5.0 10 15 -2 -0.64 -1.6 -4.2 -1.6 -0.51 -1.3 -3.4 -1.15 -0.36 -0.9 -2.4 ma
iw4029b ac electrical characteristics (c l =50pf, r l =200k , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c 25 c 125 c unit t max maximum clock frequency (figure 1) 5.0 10 15 2 4 5.5 2 4 5.5 1 2 2.75 mhz t phl , t plh maximum propagation delay, clock to q (figure 1) 5.0 10 15 500 240 180 500 240 180 1000 480 360 ns t phl , t plh maximum propagation delay, clock to carry output (figure 1) 5.0 10 15 560 260 190 560 260 190 1120 520 380 ns t phl , t plh maximum propagation delay, preset enable to q (figure 1) 5.0 10 15 470 200 160 470 200 160 940 400 320 ns t phl , t plh maximum propagation delay, preset enable to carry output (figure 1) 5.0 10 15 640 290 210 640 290 210 1280 580 420 ns t phl , t plh maximum propagation delay, carry input to carry output (figure 1) 5.0 10 15 340 140 100 340 140 100 680 280 200 ns t thl , t tlh maximum output transition time, any output (figure 1) 5.0 10 15 200 100 80 200 100 80 400 200 160 ns c in maximum input capacitance - 7.5 pf function table control input logic level action bin/dec (b/d) h l binary count decade count up/down (u/d) h l up count down count preset enable (pe) h l jam in no jam carry in (ci) (clock enable) h l no counter advance at pos. clock transition advance counter at pos. clock transition rev. 00
iw4029b rev. 00 timing requirements (c l =50pf, r l =200 k , input t r =t f =20 ns) v cc guaranteed limit symbol parameter v -55 c 25 c 125 c unit t w minimum pulse width, clock (figure 1) 5.0 10 15 180 90 60 180 90 60 360 180 120 ns t w minimum pulse width, preset enable (figure 1) 5.0 10 15 130 70 50 130 70 50 260 140 100 ns t su * minimum setup time, clock to b/d or u/d (figure 1) 5.0 10 15 340 140 100 340 140 100 680 280 200 ns t rem * minimum removal time, preset enable (figure 1) 5.0 10 15 200 110 80 200 110 80 400 220 160 ns t h ** minimum hold time, clock to carry in (figure 2) 5.0 10 15 50 30 25 50 30 25 100 60 50 ns t su minimum setup time, carry in to clock (figure 1) 5.0 10 15 200 70 60 200 70 60 400 140 120 ns t r , t f ** maximum input rise and fall times,clock (figure 2) 5.0 10 15 15 15 15 15 15 15 30 30 30 s * from up/down, binary/decode, carry in, or preset enable control inputs to clock edge. ** from carry in to clock edge
iw4029b figure 1. switching waveforms figure 2. switching waveforms rev. 00
iw4029b timing diagram; binary mode; j1=high; j2=low; bin/dec=high timing diagram; decade mode; j1=low; j4=low; bin/dec=low rev. 00
iw4029b expanded logic diagram truth table clock te pe j q q x x l l l h l h x q q x x l h h l h h x q q nc x h x q q nc rev. 00
iw4029b n suffix plastic (ms - 001bb) l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 dimensions, mm symbol min max a 18.67 19.69 b 6.10 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 j 0 10 k 2.92 3.81 l 7.62 8.26 m 0.20 0.36 n 0.38 notes: 1. imensions ?a?, ?b? do not include mold flash or protrusions. maximum mold flash or protrusions 0.25 mm (0.010) per side. d suffix soic (ms - 012ac) a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 dimensions, mm symbol . min max a 9.80 10.0 b 3.80 4.00 c 1.35 1.75 d 0.33 0.51 f 0.40 1.27 g 1.27 h 5.72 j 0 8 k 0.10 0.25 m 0.19 0.25 p 5.80 6.20 r 0.25 0.50 notes: 1.dimensions a and b do not include mold flash or protrusion. 2.maximum mold flash or protrusion 0.15 mm (0.006) per side for a, for b - 0.25 mm (0.010) per side. rev. 00
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